Self-feedback control pipeline architecture for memory read path applications

ABSTRACT

A memory reading apparatus transfers digital data from a memory array that is independent of external clocking rate, where the data transmission time is not limited by the external clock period, and the internal timing of controls permits flexible column selection and no conflicts in the timing between external clock signals and internal bit line sensing ready signal. The memory read apparatus has a data read path circuit and a memory read control apparatus. The data read path circuit is in communication with the memory to acquire the selected data read from the memory, synchronize the selected data, and transfer the selected data from the memory. The memory read control apparatus is in communications with the data read path circuit for selecting the data to be read from the memory, for providing self-feedback signals for synchronizing the selected data for transfer from the memory.

BACKGROUND OF THE INVENTION

This is a divisional application of U.S. patent application Ser. No.11/492,600 filed on Jul. 25, 2006, which is herein incorporated byreference in its entirety, and assigned to a common assignee.

1. Field of the Invention

This invention relates generally to an electronic memory devices. Moreparticularly, this invention relates to circuits for the extraction orreading of digital data from an electronic memory.

2. Description of Related Art

In present electronic memory devices an address is decoded into rowaddresses and column addresses. The row addresses activates word linesof a row within an array of memory cells. All the memory cells of therow are activated and the digital data is transferred through bit lineconnection to sense amplifiers for recovery. The column address are usedto activate bit line switches for selecting which column is to transferits recovered data to a data line sense amplifier for furtherconditioning and amplification. The output of the data line senseamplifier is applied to a data line latch for synchronization with an

This read path is structured as a three layer pipeline. The first stageis from the word line access to the bit line switch selection. Thesecond stage is the data line sense amplifier to the data line senseamplifier latch and the third stage is the data output latch.

The latency of an access of data is determined by the time from thepresentation of an address to the presence of the data at the output ofthe driver circuit. The structure of the second pipeline stage allowsfor shortening of the stage to improve the data access. If the pipelinestages (especially the second pipeline stage) are not shortened then theminimum latency is determined by the long cycle applications where datafor different word lines are accessed sequentially. However, if thepipeline stages are shortened then the data transmission time form thebit line sense to the data output latch at the third pipe line stage islimited by the maximum external clock rate.

Refer now to FIG. 1 for a more detailed discussion of a read data pathof the prior art. Memory cells 5 are arranged in rows and columns toform the sub-arrays 10 a, . . . , 10 n. An address is decoded to formthe word line addresses 15 and the bit line addresses 45 for selectingthe desired rows and columns of the memory sub-array 10 a, . . . , 10 n.Each of the memory cells 5 of a selected word line 15 is activated andthe digital data is transferred to the bit lines (BL00, BL00 , . . . ,BLmn, BLmn). The bit line sense amplifiers 22 a, . . . , 22 n acquire,amplify, and condition the digital data. The bit line switches 32 a, . .. , 32 n are connected to the terminal ends of the bit lines BL00, BL00, . . . , BLmn, BLmn to receive the digital data from the bit line senseamplifiers 22 a, . . . , 22 n. Each of the bit line switches 32 a, . . ., 32 n are formed of a pair of metal oxide semiconductor (MOS)transistors (M1 and M2). The gates of the MOS transistors (M1 and M2)are connected to receive the bit line selection signals BS 55 from thecolumn decoder 50. The column decoder is connected to the column decodecontrol circuit 40, which receives a bit line sense amplifier readysignal 35 indicating the digital data present on the bit lines BL00,BL00 , . . . , BLmn, BLmn has been sense, amplified, and conditioned fortransfer from the memory array 25. The column address 45 is decoded andone of the desired bit line switch 32 a, . . . , 32 n is activated totransfer the digital data from the memory array 25 through the bit lineswitches 32 a, . . . , 32 n to the data line sense amplifier 60. Thedata line sense amplifier 60 further amplifies and conditions thedigital data.

The output of the data line sense amplifier 60 is connected to the inputof the data line sense amplifier latch 65. The data lines senseamplifier 65 is a data storage element used to synchronize the digitaldata with an external clock for transfer to external circuitry.

The output of the data line sense amplifier 60 is transferred to theinput of the data output latch 70. The data output latch 70 is a seconddata storage element used to retain the digital data during transfer ofthe digital data through an off chip driver 75 to a data output terminalDQ 80 and to external-circuitry.

The bit line switches 32 a, . . . , 32 n form the boundary 30 of thefirst pipeline stage. The data line sense amplifier latch 65 forms theboundary of the second pipeline stage and the data output latch formsthe boundary of the third pipeline stage. As noted above, the secondpipeline stage can be shortened to minimize the latency of the firstaccess of the digital data from the memory. Thus the performance of thememory system is limited by this first access. If the pipelinetransmission time is reduced, then the performance of the memory systemis determined by the maximum clock frequency that determines the minimumtransmission time from the bit line sense amplifiers 22 a, . . . , 22 nto the output terminal DQ 80.

“A 9 Ns 16 Mb CMOS SRAM with Offset Reduced Current Sense Amplifier.”Seno, et al., Digest of Technical Papers: 40th ISSCC IEEE InternationalSolid-State Circuits Conference, 1993, pp.: 248-249, 297 describes a4-Mb×4 SRAM (static random access memory) with a current-modenonequalized read data path. The read data path has an offset-reducedstabilized-feedback current sense amplifier and a quadrant-organizationarchitecture.

U.S. Pat. No. 5,959,900 (Matsubara) illustrates a synchronoussemiconductor memory having a register with an input gate and an outputgate, for holding read-out data between the input gate and the outputgate. An input gate control circuit controls an open/close of the inputgate with a output switch feedback signal in the form of a one-shotpulse generated by an output gate control circuit for controlling anopen/close of the output gate. The open/close, in synchronism with anoutput gate switch signal, so that only after the data held in theregister has been transferred to an external of the register, the nextdata to be successively transferred from the read/write bus to theregister is actually latched in the register.

U.S. Pat. 6,452,865 (Wolford) provides a single common symmetricaldouble data rate (DDR) synchronous random access memory (SDRAM) readdata path structure and corresponding storage addressing scheme. Theread data path structure implements both an N-bit interface and an(N/2)-bit interface to the DDR memory. The read data path structure usesa feedback loop of a lower data path to a higher data path inconjunction with the translation of the physical addressing of the datastored into a memory. The feedback loop and address translationmechanism is enabled for (N/2)-bit mode and disabled for N-bit mode.

U.S. Pat. No. 6,539,454 (Mes) describes an asynchronously pipelinedSDRAM. The asynchronously pipelined SDRAM has separate pipeline stagesthat are controlled by asynchronous signals to synchronize data at eachstage, an asynchronous signal is used to latch data at every stage. Theasynchronous control signals are generated within the chip and areoptimized to the different latency stages. The data is synchronized tothe clock at the end of the read data path before being read out of thechip.

SUMMARY OF THE INVENTION

An object of this invention is to provide a data reading apparatus fortransferring digital data from a memory array that is independent ofexternal clocking rate.

Another object of this invention is to provide a data reading apparatusfor transferring digital data from a memory array where the datatransmission time is not limited by the external clock period.

Another object of this invention is to provide a data reading apparatusof transferring digital data from a memory array such that internaltiming of controls permits flexible column selection and no conflicts inthe timing between external clock signals and internal bit line sensingready signals.

To accomplish at least one of these objects, a memory read apparatuswithin a memory system is in communication with an array of memory cellsfor transferring selected data read from the memory. The memory readapparatus has a data read path circuit and a memory read controlapparatus. The data read path circuit is in communication with thememory to acquire the selected data read from the memory, synchronizethe selected data, and transfer the selected data from the memory. Thememory read control apparatus is in communications with the data readpath circuit for selecting the data to be read from the memory, forproviding self-feedback signals for synchronizing the selected data fortransfer from the memory.

The data read path includes a plurality of bit line switches incommunication with bit line sense amplifiers within the array of memorycells for selectively transferring the data from selected memory cells.A data line sense amplifier in communication with the plurality of bitline switches to receive the data from the selected memory cell. A dataline sense amplifier latch is in communication with data line senseamplifier to acquire the data for synchronization and a data outputlatch is in communication with the data line sense amplifier latch tosynchronously transfer the data from the memory.

The memory read control apparatus has a data output latch controlcircuit receiving an external timing signal to provide a timing signalto the data output latch for synchronization of the transferring of theselected data from the memory. A sense amplifier latch control circuitis in communication with the data output latch control circuit toreceive a sense amplifier latch clear signal to provide a senseamplifier latch control signal to the data line sense amplifier latch tosynchronize the selected data read from the memory comprising. A senseamplifier control circuit is in communication with the data line senseamplifier to provide a data line sense amplifier enabling signal to thedata line sense amplifier and with the sense amplifier control circuitto provide a sense amplifier enable signal to the sense amplifier latchcontrol circuit and receive the sense amplifier latch signal from thesense amplifier latch control circuit to indicate that the data linesense amplifier is to be disabled.

The memory read path apparatus further has a column control circuit incommunication with the sense amplifier control circuit to receive a readsynchronization signal. The column control circuit is further incommunication with the memory to receive a bit line sense ready signalto generate a bit line switch enable signal, and with a column addressdecoder with the memory to provide a bit line switch activation signalfor selecting a desired data for transfer from the memory.

The memory array may be such memories as a pseudo-static random accessmemory, static random access memory, read only memory, or dynamic randomaccess memory.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic diagram of a memory device illustrating the dataread path circuitry of the prior art.

FIG. 2 is a schematic diagram of a memory device illustrating the dataread path circuitry of this invention.

FIG. 3 is a schematic diagram of a memory device illustrating the dataread path circuitry of this invention highlighting the self-feedbackcontrol paths.

FIG. 4 is a timing diagram of the operation of the memory device withthe data read path circuitry of this invention.

DETAILED DESCRIPTION OF THE INVENTION

The data read path circuitry within a memory system of this inventioncontrols and synchronizes a memory read operation for transferringselected data read from the memory. The data read path circuitryreceives an external timing or clock signal and generates a data outputlatch timing signal from the external timing signal. The data outputlatch timing signal is transferred to a data output latch forsynchronization of the transferring of the selected data from thememory. The external timing or clock signal is used to generate a senseamplifier latch clear signal that is then combined with a sensesamplifier enable signal to produce the sense amplifier latch controlsignal. The sense amplifier latch control signal is then transferred toa sense amplifier latch of the memory to gate the selected data readfrom the memory.

A column decode circuit receive a column address, decodes the address togenerate the bit switch activation signals to activate bit switches ofeach column of the array of memory cells to select one of the outputs ofthe bit line sense amplifiers to a data line sense amplifier. The bitswitch enable signal is used to generate a data line sense amplifierenable signal. The sense amplifier latch control signal is used to stopthe data line sense amplifier enable signal to deactivate the data linesense amplifier.

A read synchronization signal generated from a combination of the bitline switch enable signal and the sense amplifier latch control signal.A bit line sensing ready signal is received from the array of memorycells when the bit lines have been retrieved by the sense amplifiers.The read synchronization signal and bit line sensing ready signal arecombined to generate one of the bit switch activation signals forselecting a desired data for transfer from the memory.

Refer now to FIG. 2 for a more detailed discussion of a read data pathof a memory device of this invention. In a structure similar to those ofFIG. 1, the memory cells 105 are arranged in row and columns to form thesub-arrays 110 a, . . . , 110 n. An address is decoded to form the wordline addresses 115 and the bit line addresses 145 for selecting thedesired rows and columns of the memory sub-array 110 a, . . . , 110 n.Each of the memory cells 105 of a selected word line 115 is activatedand the digital data is transferred to the bit lines (BL00, BL00 , . . ., BLmn, BLmn). The bit line sense amplifiers 122 a, . . . , 122 nacquire, amplify, and condition the digital data. The bit line switches132 a, . . . , 132 n are connected to the terminal ends of the bit linesBL00, BL00 , . . . , BLmn, BLmn to receive the digital data from the bitline sense amplifiers 122 a, . . . , 122 n. Each of the bit lineswitches 132 a, . . . , 132 n are formed of a pair of metal oxidesemiconductor (MOS) transistors (M1 and M2). The gates of the MOStransistors (M1 and M2) are connected to receive the bit line selectionsignals BS 155 from the column decoder 150. The column decoder isconnected to the column control circuit 140, which receives a bit linesensing ready signal 135 indicating the digital data present on the bitlines BL00, BL00 , . . . , BLmn, BLmn has been sensed, amplified, andconditioned for transfer from the memory array 125. The column address145 is decoded and the desired bit line switch 132 a, 132 n is activatedto transfer the digital data from the memory array 125 through the bitline switches 132 a, . . . , 132 n to the data line sense amplifier 160.The data line sense amplifier 160 further amplifies and conditions thedigital data.

The output of the data line sense amplifier 160 is connected to theinput of the data line sense amplifier latch 165. The data lines senseamplifier latch 165 is a data storage element used to synchronize thedigital data with an external clock for transfer to external circuitry.

The output of the data line sense amplifier latch 165 is transferred tothe input of the data output latch 170. The data output latch 170 is asecond data storage element used to retain the digital data duringtransfer of the digital data through an off chip driver 175 to a dataoutput terminal DQ 180 and to external circuitry.

The bit line switches 132 a, . . . , 132 n form the boundary 130 of thefirst pipeline stage. The data line sense amplifier latch 165 forms theboundary of the second pipeline stage and the data output latch formsthe boundary of the third pipeline stage. The external clock 185 isapplied to a data output control circuit 190 to generate the data outputlatch timing signal 195 to control the activation of the data outputlatch 170 for transfer of the data to the off chip driver 175 to thedata output terminal DQ 180. The data output control circuit 190 furthergenerates a data line sense amplifier latch clear signal 200. The dataline sense amplifier latch clear signal 200 and a data line senseamplifier enable signal 220 are combined in the sense amplifier latchcontrol circuit 205 to generate the data line sense amplifier latchcontrol signal 210.

The data line sense amplifier latch control signal 210 is transferred tothe data line sense amplifier control circuit 215. The data line senseamplifier latch control signal 210 is combined with the bit line switchactivation signals 155 to generate the data line sense amplifier enablesignal 220. The data line sense amplifier latch control signal 210 isfurther combined with the bit line switch enable signal 230 to generatethe read synchronization signal 225 that is applied to the columncontrol circuit 140.

The bit line sensing ready signal 135 is an input to the column controlcircuit 140 and is combined with the read synchronization signal 225 togenerate the bit line switch enable signal 230. The bit line switchenable signal is combined with the bit line addresses 145 to activatethe appropriate bit switch activation signal 155 at its appropriatetime.

FIG. 3 shows the data read path structure of the memory device of thisinvention and highlights the self-feedback control paths of the pipelineof the data read path. The first feedback control path 250 synchronizesthe bit line switch enable signals 155 such that they are activatedbased ultimately on the external clock 185 and the bit line sensingready signal 135. The second feedback control path 255 provides thetiming for the data line sense amplifier enable signal 220 and the dataline sense amplifier latch control signal 210. The basic control path(control path 3) 260 provides the timing for the third pipeline stage.When the current data present DT2 at the data line sense amplifier latch165 is latched to the data output latch 170, the data line senseamplifier latch 165 can be release and made ready for the next data DT1from the data line sense amplifier 160.

Refer now to FIG. 4 for a discussion of the function of the firstfeedback control path 250, second feedback control path 255, and thebasic control path 260. The bit line sensing ready signal 135 is broughtto an active state at a time after one of the transitions of theexternal clock 185, as determined by the latency of the access of thememory array. The bit switch enable signal 230 is activated based on thetransition of the bit line sensing ready signal 135 which in turn actsto activate one of the selected the bit line switch activation signals155 to turn on one of the bit line switches 132 a, . . . , 132 n ofFIGS. 2-3. The first feedback control path 250 of FIG. 3 provides thecontrol of the active interval time for the bit line switches 32 a, . .. , 32 n to transfer the selected digital data to the data line senseamplifier 160 of FIGS. 2-3. The first segment (*a) of the feedbackcontrol path 250 activates the data line sense amplifier enable signal220 for the transfer of the selected data signals to the data line senseamplifier 160. The duration of the first segment (*a) tracks the timetaken for the data line sense amplifier 160 to develop the digital dataDT1 at its output. This determines the amount of time that the data linesense amplifier enable signal 220 is active after the selected bit lineswitches 132 a, . . . , 132 n is activated to effectively connect theselected bit line BL00, BL00 , . . . , BLmn, BLmn to the data line senseamplifier 160. The second segment (*b) and the third segment (*c)determines the time at which the read synchronization signal 225 isactivated and from the read synchronization signal 225, the bit lineswitch enable signal 230 and thus the bit line switches 132 a, . . . ,132 n are deactivated as quickly as possible.

The second feedback control path 255 begins with the data line senseamplifier enable signal 220 determine the time at which the data linesense amplifier latch control signal 210 is activated to capture thedata into the data line sense amplifier latch 165 of FIGS. 2-3 duringthe first segment (*d). In the prior art, the data line sense amplifier60 of FIG. 1 was deactivated or reset by the external clock 85. Thisforces the data at the output of the data line sense amplifier latch 65to be held until it the data output latch 70 is activated or set.

The data line sense amplifier latch control signal 210 determines thetime at which the data line sense amplifier enable signal 220 isdeactivated to disable the data lines sense amplifier 160 during thesecond segment (*e). This in turn determines the time at which the nextread cycle is initiated. In the third segment (*f), the readsynchronization signal 225 is set to a level which allows the bit lineswitch enable signal 230 to be activated and the next bit line switch132 a, . . . , 132 n to be activated again.

The third pipeline includes the segments *g and *h to control thecapturing of the digital data DT2 in the data line sense amplifier latch165 and the reset or release of the data line sense amplifier latch 165.In the segment *g, the external clock triggers the data line senseamplifier latch clear signal 200.

The data output latch timing signal 195 is adjusted by the data outputcontrol circuit 190 to account for the memory latency. The mode registercode 191 provides a user defined code that adjust the latency cycles ofthe data output latch timing signal 195.

The data line sense amplifier latch clear signal 200 then determines thetime for the deactivation or reset of the data line sense amplifierlatch 165. This permits the acquisition of the next data DT2 by the dataline sense amplifier latch 165.

The self-feedback structure of the read data path control circuitry ofthis invention provides an internal timing margin that is independent ofthe frequency of the external clock 185. Further, the structure providesa relatively simple solution that is easily implemented in an integratedcircuit. This provides more flexibility relative to that of the priorart where the data transit time for each stage is limited by the periodof the external clock 185.

This structure is suitable for static random access memory, read onlymemory, or dynamic random access memory. However, this structure isparticularly suitable for pseudo-static random access memory because itlacks a clear column read command at each read cycle. This prevents anyproblems of boundary alignment of the data access where overlap of theexternal clock 185 and the bit line sensing ready signal 135.

While this invention has been particularly shown and described withreference to the preferred embodiments thereof, it will be understood bythose skilled in the art that various changes in form and details may bemade without departing from the spirit and scope of the invention.

1. A memory read path apparatus in communication with an array of memorycells for transferring selected data read from said memory comprising: adata read path circuit in communication with said memory to acquire saidselected data read from said memory, synchronize said selected data, andtransfer said selected data from said memory; and a memory read controlapparatus in communications with said data read path circuit forselecting said data to be read from said memory, for providingself-feedback signals for synchronizing said selected data for transferfrom said memory.
 2. The memory read path apparatus claim 1 wherein saiddata read path comprises: a plurality of bit line switches incommunication with bit line sense amplifiers within said array of memorycells for selectively transferring said data from selected memory cells;a data line sense amplifier in communication with said plurality of bitline switches to receive said data from said selected memory cells; adata line sense amplifier latch in communication with data line senseamplifier to acquire said data for synchronization; and a data outputlatch in communication with said data line sense amplifier latch tosynchronously transfer said data from said memory.
 3. The memory readpath apparatus of clam 2 wherein said memory read control apparatuscomprises: a data output latch control circuit receiving an externaltiming signal to provide a timing signal to said data output latch forsynchronization of the transferring of the selected data from saidmemory; a sense amplifier latch control circuit in communication withsaid data output latch control circuit to receive a sense amplifierlatch clear signal that is combined with a data line sense amplifierenable signal to generate a sense amplifier latch control signal that iscommunicated to said data line sense amplifier latch to synchronize theselected data read from said memory; and a sense amplifier controlcircuit in communication with said sense amplifier latch control circuitto provide said data line sense amplifier enable signal to said senseamplifier latch control circuit and to receive said sense amplifierlatch control signal from said sense amplifier latch control circuit andin communication with a data line sense amplifier to provide a data linesense amplifier enabling signal to said data line sense amplifier and tosaid sense amplifier latch control circuit and receive the senseamplifier latch signal from said sense amplifier latch control circuitto indicate that said data line sense amplifier is to be disabled. 4.The memory read path apparatus of claim 3 further comprising a columncontrol circuit in communication with said sense amplifier controlcircuit to receive a read synchronization signal, with the memory toreceive a bit line sensing ready signal to generate a bit line switchenable signal, and with a column address decoder within the memory toprovide a bit line switch enable signal for selecting a desired data fortransfer from said memory.
 5. The memory read path apparatus of claim 4wherein said sense amplifier control circuit receives said bit lineswitch enable signal from said address control circuit and wherein saidbit line switch enable signal is combined with said sense amplifierlatch control signal to generate said data line sense amplifier enablingsignal
 6. The memory read path apparatus of claim 3 wherein said memoryis selected from the group of memories consisting of pseudo-staticrandom access memory, static random access memory, read only memory, anddynamic random access memory.